Semiconductor fabrication involves the creation of the desired pattern into a layer or layers of material. Creation of the desired pattern into a specific layer involves a pattern transfer process that utilizes masks in combination with conventional etching processes such as optical lithography and sidewall image transfer (SIT). The need for the creation of desired patterns having pitches of 26 nm or less and nodes of 10 nm or less including both two-dimensional and three-dimensional patterns exposes the limitations of conventional methods for image creation and transfer. For example, a block cut is needed for both mandrel and non-mandrel metals wires. However, block pattern overlay is a continuing problem as the pattern pitch decreases. Existing block masks will cut wires that do not need to be cut. In addition, tall spacers cause pitch walking, and existing processes can damage spacers and mandrel materials. Therefore, a semiconductor fabrication process is desired that compensates for the limitation of a 40 nm pillar size, overlay shift and critical dimension uniformity.